Job Summary
- Company
- AMD
- Location
- Boxborough, MA 01719
- Industries
- Electronics, Components, and Semiconductor Mfg
- Job Type
- Full Time
- Employee
- Years of Experience
- 5+ to 7 Years
- Education Level
- Bachelor's Degree
- Career Level
- Experienced (Non-Manager)
- Job Reference Code
- 7345
Sr SRAM Verification Engineer 7345
About the Job
Sr SRAM Verification Engineer will be responsible for validating SRAM BIST processor architectures within AMD’s microprocessor and graphics products and test chips.
A successful candidate should be able to become an AMD embedded SRAM BIST processor architecture expert over time, and is expected to create appropriate test programs to detect faults in embedded memories. This work will include interfacing with both silicon design and product development engineers to co-develop appropriate tests, overseeing the execution of those tests on product and test chip samples, and diagnosing faults that are detected. This work will also include generating and validating ATPG test patterns that will be used by AMD's product development engineering efforts.
Skills, Education and Experience Requirements:
Candidate should have 3-5 years experience in writing and verifying RTL models of digital integrated circuits. Specific knowledge and experience writing and verifying SRAM BIST-related RTL models is preferred. Prior exposure to Virage Logic's SMS BIST processor architectures is a plus. Knowledge of and prior experience in ATPG tools is also a plus. Knowledge of scripting languages such as PERL, TCL, Python, etc. is a requirement. An MSEE is preferred.
A successful candidate should be able to become an AMD embedded SRAM BIST processor architecture expert over time, and is expected to create appropriate test programs to detect faults in embedded memories. This work will include interfacing with both silicon design and product development engineers to co-develop appropriate tests, overseeing the execution of those tests on product and test chip samples, and diagnosing faults that are detected. This work will also include generating and validating ATPG test patterns that will be used by AMD's product development engineering efforts.
Skills, Education and Experience Requirements:
Candidate should have 3-5 years experience in writing and verifying RTL models of digital integrated circuits. Specific knowledge and experience writing and verifying SRAM BIST-related RTL models is preferred. Prior exposure to Virage Logic's SMS BIST processor architectures is a plus. Knowledge of and prior experience in ATPG tools is also a plus. Knowledge of scripting languages such as PERL, TCL, Python, etc. is a requirement. An MSEE is preferred.
